The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A signal path between a transmitter and a receiver (e.g., a receiver path of a serial data interface) includes a communication channel. For example, the serial data interface may be a high speed serial data interface. A signal transmitted via the communication channel may be modified by noise, interference, and/or frequency-dependent attenuation and dispersion. Frequency-dependent attenuation can introduce distortions into the transmitted signal. For example, the distortions may include inter-symbol interference (ISI) and jitter. The distortions may cause errors in the signal as received by the receiver.
The communication channel may be implemented using differential signaling. Differential signaling can reduce the effects of some forms of interference, such as common mode noise. Equalizers such as Continuous Time Linear Equalizers (CTLEs) may be used in communication channels to partially compensate for channel attenuation. A CTLE may be implemented as a differential amplifier with a fixed or programmable frequency dependent degeneration feature. The CTLE may be followed by a summing node and a high-speed latch in the communication channel.
FIG. 1 shows a receiver path 100 (e.g., of a serial data receiver) including a communication channel 104, an equalizer 108, a sampler 112, a summer 116, a decision feedback estimation (DFE) module 120, and a high-speed latch 124. The equalizer 108 may be, for example, a switched continuous time linear equalizer (CTLE) or a switched CTLE with an integrated sampler.
The equalizer 108 receives an input signal 128 via the communication channel 104 and generates an output signal 132. Each of the input signal 128 and the output signal 132 may include a differential signal pair. The equalizer 108 performs equalization on the input signal 128 to generate the output signal 132. For example, the equalizer 108 may include a differential amplifier.
The input signal 128 received from the communication channel 104 may include attenuation (e.g., frequency dependent attenuation). For example, the frequency dependent attenuation caused by skin effect and dielectric loss, which are two possible sources of attenuation in the communication channel 104, is proportional to a square root of a frequency and the frequency, respectively. The equalizer 108 compensates for any attenuation in the input signal 128 to generate the output signal 132.
The sampler 112 samples the output signal 132 to generate a sampled signal 136. The summer 116 receives the sampled signal 136 and an output 140 of the DFE module 120. For example, the summer 116 may add one or more signals corresponding to a digital output 144 of the high-speed latch 124 to the sampled signal 136 or subtract one or more signals from the sampled signal 136. The high-speed latch 124 receives an output 148 of the summer 116 and determines a digital value corresponding to the input signal 128. Accordingly, the digital output 144 of the high-speed latch 124 is, for example, a digital high (e.g., “1”) or a digital low (e.g., “0”). In some implementations, the high-speed latch 124 may determine a multi-bit digital value that corresponds to the input signal 128 and generate a corresponding multi-bit digital output 144. In some implementations, the summer 116 and the DFE module 120 may be omitted and the equalizer 108 is instead connected directly to the slicer high-speed latch 124
FIG. 2 shows a high-speed latch 200. The latch 200 receives a differential analog input signal 204 (e.g., differential inputs 204-1 and 204-2 corresponding to the output 148 as shown in FIG. 1) and generates a differential digital output signal 208 (e.g., differential outputs 208-1 and 208-2 corresponding to the digital output 144 as shown in FIG. 1). For example, an input amplifier 212 receives the analog input signal 204. A tail current source 216 outputs a current based on, for example, a first bias voltage 220 and a second bias voltage 224, and a voltage source 228. The input amplifier 212 selectively provides current to an output circuit 232 based on the current received from the tail current source 216 and the analog input signal 204. The output circuit 232 generates the digital output signal 208 based on the current received from the input amplifier 212. The output circuit 232 may include a reset node 236 for resetting the output circuit 232.